The field of IC design has advanced to allow designers to rapidly design and verify circuits, with extensive use of standard, reusable components and design flows. Electronic design automation (EDA) tools allow the designer to develop a design at a relatively high level of abstraction (e.g., register-transfer-level (RTL) or gate-level), generate a transistor-level schematic level design, and verify performance at the transistor level (a pre-layout simulation). Then the tool generates a layout and performs various verification tasks. The circuit designer runs design rule checks (DRC) and layout-versus-schematic (LVS) checks. After the layout is “DRC and LVS clean,” the circuit designer runs resistance-capacitance (RC) extraction to obtain the parasitic capacitance values from the layout. The overall circuit performance including layout parasitics is finally obtained by running the post-layout simulation.
Parasitics (computed during RC extraction) are carefully taken into account when high-precision and/or high-speed circuits are laid out. In nanometer CMOS designs, parasitic loading and cross-talk effects can seriously degrade circuit performance. These effects can include gain-bandwidth, frequency, setup/hold time, and slew rate. If the post-layout simulation indicates that the layout does not meet performance specifications when the parasitic capacitances are taken into account, the designer may make a change to the front-end (active device layer) design and repeat the verification analysis, which is time consuming.